RISC-V System-on-Chip Design

David Harris · James Stine · Sarah Harris · Rose Thompson

2026年5月 · Elsevier

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600

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RISC-V System-On-Chip Design fits at the nexus of computer architecture, microarchitecture, and chip design. It is written to be accessible to an advanced undergraduate audience with limited background. It explains concepts from operating systems, VLSI, and memory systems as necessary, and high school mathematics is sufficient preparation for most of the book, although the floating point and division chapters will be primarily of interest to those with a curiosity about computer arithmetic. Like Harris and Harris's Digital Design and Computer Architecture textbooks, this book will appeal to students with easy-to-read and complete explanations, sidebars, and occasional humor and cartoons.It comes with an open-source implementation and will include end-of-chapter problems to extend the RISC-V processor in various ways. Ancillary materials include a GitHub repository with complete open-source SystemVerilog code, validation code in C and assembly language, and code for benchmarking and booting Linux.Ancillary materials include a GitHub repository with complete open-source SystemVerilog code for the fully-functional Wally RISC-V SoC, validation code in C and assembly language, code for benchmarking and booting Linux, labs, slides, exercises, and figures.Please note that chapters 20-23 and Appendices A-D and F are not included in the print book but are available on the Companion Site athttps://shop.elsevier.com/books/book-companion/9780323994989. These chapters and appendices are also in the electronic version of the book.Supplementary resources for the book are also available on a website hosted by the authors at: ddcabook.com. - Includes a concrete application & implementation of the open RISC-V architecture - Explores rarely taught microarchitectural issues: - Pipelines, buses, caches, branch prediction, virtual memory, floating-point, cryptography & peripherals - Illustrates system design with CORE-V Wally, a fully functional RISC-V system-on-chip: - Programming & debugging RISC-V in C & assembly - SystemVerilog design, debug, verification & synthesis - Benchmarking - Booting Linux on a simulator & FPGA - Provides complete open-source code: github.com/openhwgroup/cvw

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作者简介

David Harris is the Harvey S. Mudd Professor of Engineering Design at Harvey Mudd College. He received his Ph.D. in electrical engineering from Stanford University and his M.Eng. in electrical engineering and computer science from MIT. Before attending Stanford, he worked at Intel as a logic and circuit designer on the Itanium and Pentium II processors. Since then, he has consulted at Sun Microsystems, Hewlett-Packard, Broadcom, and other design companies. David holds more than a dozen patents and is the author of three other textbooks on chip design, as well as many Southern California hiking guidebooks. When he is not working, he enjoys hiking, flying, and making things with his three sons.James Stine is the Edward Joullian Professor of Engineering at Oklahoma State University. His area of research is in computer arithmetic, memory architectures, and Electronic Design Automation (EDA) design flow. He is the author of numerous articles on optimization of architectures for use with computer arithmetic as well as interfacing to memory architectures. He is the author of three texts: Digital Datapath Computer Arithmetic with Verilog, Adder Architectures for VLSI Implementations and System on Chip Design Flow and Standard-Cell Library.Sarah L. Harris is an Assistant Professor of Engineering at Harvey Mudd College. She received her Ph.D. and M.S. in Electrical Engineering from Stanford University. Before attending Stanford, she received a B.S. in Electrical and Computer Engineering from Brigham Young University. Sarah has also worked with Hewlett-Packard, the San Diego Supercomputer Center, Nvidia, and Microsoft Research in Beijing. Sarah loves teaching, exploring and developing new technologies, traveling, wind surfing, rock climbing, and playing the guitar. Her recent exploits include researching sketching interfaces for digital circuit design, acting as a science correspondent for a National Public Radio affiliate, and learning how to kite surf. She speaks four languages and looks forward to learning more in the near future.Rose Thompson is a processor architect at Skyworks Solutions, Inc. She received her Ph.D. in Electrical Engineering from Oklahoma State University and two B.S. degrees in Electrical Engineering and Computer Engineering from the University of Washington. She has also designed chips at the Air Force Research Laboratory. Her professional interests include SoC design and verification, custom instruction set architectures, branch prediction, memory systems, and secure computing. Rose also enjoys biking, hiking, rock climbing, and playing the piano.